Voltage-controlled or current-controlled delay cells have numerous applications in circuit design. In delay-locked loops (DLLs) a cascade of delay cells forms a delay line that is controlled through feedback action by a charge pump and/or a phase detector to set the overall delay to a specific value. Controllable-delay cells are also used in ring oscillators. Multi-stages DLLs or ring oscillators are used to generate multi-phase signals. Multi-stage DLLs are further used to implement a frequency divider or multiplier with a fractional division or multiplication ratio, for example, by using a multiplexer known as an edge-combiner.
In typical implementations, process variations may produce considerable mismatches between the multiple delay cells that form the DLL or the ring oscillator. This may cause an error in the different phases generated through the DLL or ring oscillator. For example, a mismatch in the delay of the stages may cause frequency spurs. Furthermore, if the phase difference between the various outputs is not equal, a periodic time error may appear at the output. These spurs may substantially limit the application of the DLL as a frequency divider/multiplier where high spectral purity clock is required. For example, if one of the multiple delay cells exhibits a delay mismatch of approximately 10 percent, the power of the output spur would be approximately −32 dBc (namely, approximately 0.32 decibels below the carrier). However, some wireless communication standards may require spurs to be as low as −65 dBc for the local oscillator.